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Honored Contributor
Honored ContributorLoss of FPGA configuration
To minimize power consumption, I have the Oscillator input of the main part of my Stratix III design gated (glitchfree keeping low, if gated). Connected to this clock (50 MHz) are two synchron...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I wonder, if the current transient may be normal operation and the voltage drop primarly a board hardware problem. --- Quote End --- Actually, this was it. A little embarassing for me, but I stopped the power supply synchronisation as well, when going to sleep mode (and so having a weakness in supply at the begin of the sleep mode). Using a clock that doesn't stop makes the sleep mode work perfectly, even when just gatinng the input clock. Additionally putting the DDR I/F into reset state prior to the ghating is even slighly better from a consumption point of view. Sorry for bothering you about this, the hints were great help just the same!
