Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Loss of FPGA configuration

To minimize power consumption, I have the Oscillator input of the main part of my Stratix III design gated (glitchfree keeping low, if gated). Connected to this clock (50 MHz) are two synchron...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

--- Quote Start ---

To get clarity about the effect, I would either measure the respective supply rail dynamic current or check the power supply transient response with a test load.

--- Quote End ---

I'm going to do that in near future.

In meantime: Which dynamic current peaks would you expect putting a PLL into reset mode without gating it's input clock?

Actually, the same 2.5V supply I use for VCCPD powers VCC_CLKIN3C/4C/7C/8C, too. According to spec, these supplies may draw up to 250mA each. May this be the hot spot in question?