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Altera_Forum
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14 years ago

Loss of FPGA configuration

To minimize power consumption, I have the Oscillator input of the main part of my Stratix III design gated (glitchfree keeping low, if gated). Connected to this clock (50 MHz) are two synchron...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I think neither the memory IP nor the RAM hardware is intended to work with this kind of clock gating. Problems, e.g. suspected excessive current consumption will surely not occur in the PLL and also unlikely in the FPGA core, but likely in the internal or external peripherals.

Did you try to stop the affected system parts, including the PLL with an asynchronous reset? This would also make clock gating needless.