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Altera_Forum
Honored Contributor
Honored ContributorLoop index overflow problem
Hi there, I've wrote a little VHDL program in Quartus II. I'd like to separate one big std_logic_vector into small fix-length std_logic_vectors and the compile told me that the index is out...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Ok - It was because you had included the clock in the sensitivity list and not used it - it is a common newbie mistake. --- Quote End --- i think at the synthesis phase, the compile actually add all the signals to the sensitive list.
