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Altera_Forum
Honored Contributor
Honored ContributorLoop index overflow problem
Hi there, I've wrote a little VHDL program in Quartus II. I'd like to separate one big std_logic_vector into small fix-length std_logic_vectors and the compile told me that the index is out...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Then your design is very flawed. It is not going to produce synchronous logic because you have not included the clock inside your process. --- Quote End --- :D, no ,i use two processes method, this is only the combinational part, i have deleted the sequential part...
