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KhaiY
ContributorHello, I am completing port to Xilinx Spartan, to do so I teared down all QSYS logic and rewrote some part of IP core.
It is no more using Avalon is not supported on, use instead native block, it seems not suffering none of issue experienced. The one are here are justified I don't know about, Its since long long time I migrated to Altera, Xilinx and Lattice too changed a lot and actual family are new to me.
I am rewriting IP as platform/vendor neutral to isolate issue. Actual issue are not similar to what I encountered on MAX10, just fresh code is not as clean as the old one used for years no more Avalon/Qsys oriented.
Think it took few day more to complete.
ContributorStatus Update:
Porting to Spartan 6 complete.
During port I observed QSYS generate a lot of polarity invert to same signals, inserted a lot of adapter too. No idea why spreading invert across nested modules nor what is inside due it is scrambled preventing dissection.
Removed all interconnection from QSYS, so now Avalon bus is just driven by a simulated one: simple 6 way address and data multiplexer. Arbitration is driven by a simple round robin 2 queue VHDL ONLY state machine. This same deterministic SM is tight coupled to multiplexer.
No issue were present, wait status is clean, all other signals clean also without constraint. Logic was pipelined a lot on before port in the far past. High speed part IP Core locking or behaving weird on MAX 10 run fine on Spartan 6 tested @300MHz.
T80 boot up then stop on code protection but has it reason on limited RAM resources of model used. Next Xilinx step is to get a board with on board ram to assign full resources than minimal permitted by block ram.
T80 on Altera appeared to run fine when wait fixed to 1 but LCD Ip core locked and scrambled on Ram access. T80 was ok accessing ram. This can infer possible doubt about SVerilog fabric or mixed language issue. QSYS forever add SVerilog modules. Scrambled source limit further test on my side.
Future evaluation can be done on Lattice ICE40 part too, MAX10 raised too much pricing.
Next step to isolate issue is to port back this new design to Altera board and test again leaving Verilog and QSYS free. Too much time and effort was on board manufacture and test. Ready to sell since y17 never useable after first prototype from version 15.x and ES part.
