Logic Reset Input at Cyclone IV FPGA

Using a dedicated input pin was an important consideration on older generation FPGA families. Its less of an issue now since fabric signals can drive the global clock networks.

I've often seen the DEV_CLRn pin used, so that if the end-user wants, they can use that pin for the device wide reset (which does not show up in your top-level entity port list).

However, given that you should always synchronize the reset to each clock domain in your design (asynchronous assertion, synchronous deassertion) there is no advantage to using any particular pin on the FPGA.

I recommend you route the push-button signal through a reset supervisor IC. That IC will 'debounce' the push-button and ensure your logic sees one transition on the reset.

I also like to route the CONF_DONE signal to the reset supervisor, so that reset is asserted each time the FPGA configures, eg., see p95

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf

Cheers,

Dave