Forum Discussion
Altera_Forum
Honored Contributor
15 years agoLast bits of config. bitstream are ignored in Passive Serial Configuration
Hello, i am trying to configure Cyclone III (EP3C25E144C8) fpga via Passive Serial configuration method. I send all bitstream data to the fpga, but as you see on the image below, last 9 (or 10) bi...
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- I don't use a host device. I use a MCU for reading the bitstream from a spi flash memory and programming the fpga. --- Quote End --- That's exactly what I meant with 'host' --- Quote Start --- I see that last bits exist in the .rbf file and also in the .hexout file. --- Quote End --- This is a common practice. Configuration files are generated with pad bits, so that the programming device doesn't need to bother to add them. --- Quote Start --- Also, on the PS configuration datasheet, it is written that 2 more DCLK pulses are needed after Config Done pin is High to enter Initialization Mode. --- Quote End --- I don't think those are really needed for CIII. From config_done to user mode (when init_done goes high), the startup sequence is driven by the internal clock, 3185 cycles required.