Keeping output pin low while unpowered or unconfigured

Yes, that is what I want, so I filled in actual resistor values that would fit these criteria (in a worst-case scenario), and I'm rather unhappy with how far away the signal levels are from the supply rails, how little tolerance I have for the resistor values and how much drive current I need in the FPGA -- so I'm wondering if I've overlooked something.

I get much better values for normal operation if I calculate with the typical rather than minimum resistance of the internal pull-up, but if in series production I happen to get an FPGA with a stronger pull-up, I end up with a board that will activate the FET during the configuration phase, which is not the safe state of the machine as a whole, so I wouldn't sign off on that as production ready.