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Altera_Forum
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14 years ago

Keeping I/O pins to GND during power up

Hello everybody from southern Germany, I am using a CPLD in a design which drives 4 fullbridge mosfet drivers , and thus while the system is powering up I need to ensure that the I/O's whic...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Use an isolator (optic or magnetic i.e. ADUM3440) between the FPGA and the mosfet driver.

Only enable the isolator after the FPGA has powered up.

The advantage of the iso is that it protects your FPGA.