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Unfortunately, the other side of the backplane is already done and provides all the needed voltages (but no 1V or 3.0V). There is no space on the new board to add LDOs for that.
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You do not need the 1V, the buffers provide it. As for the 3.0V, I was talking about the JTAG VCCIO supply. You'd use the same supply to power the buffers.
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Probably I can use the tinylogic and add current limiting resistors on their output (they drive out up to 24mA). I can put the chip within 1" of the FPGA, so there may not be any issues with over/undeshoot. With this, I will not need clamping diodes. Does that make sense?
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The resistor on the output would be a source termination resistor, rather than a current limiting resistor. With that source termination correctly sized, there will be no overshoot. I'd recommend that approach.
Cheers,
Dave
Honored Contributor
