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Altera_Forum
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15 years ago

JTAG to Avalon master bridge usage

Hi, The main issue i want to ask is whether the jtag to avalon master bridge IP core can be used to communicate data between PC and the FPGA, even if the board does not have JTAG connector. My ...
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Altera_Forum
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15 years ago

Thank you for replying,

I do not want the address to get messed up internally. How am I supposed to make sure that I am not using native addressing? Am I supposed to use byteenable?

By default byteenable for master is 4 bits and for my design the byteenable for conduit slave is 2 bits. Do I have to set a value to the byteenable or the system will understand that I am setting the master byteenable to "0011"? I tried doing it, but this gives the same result.

Or if I make my readdata and writedata of slave to be 32 bits then I need to set the byteenable to 0011. But byteenable is an input signal within qsys system. Where can I set a value for byteenable?