Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

JTAG to Avalon master bridge usage

Hi, The main issue i want to ask is whether the jtag to avalon master bridge IP core can be used to communicate data between PC and the FPGA, even if the board does not have JTAG connector. My ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The first thing I would check if you're getting this kind of error is that your clocks are running and resets are releasing properly. If the first access fails that is normally the cause.

You can use the jtag_debug commands to do this, or if that doesn't help then I'd go for SignalTap next.