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Altera_Forum
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14 years ago

Jtag signal integrity program

Hi all: I have develop a custom board of stratix iv gx, with jtag and AS configuration. I find: 1) One week before, I can debug the fpga through jtag with USB-blaster cable(Rev C), and con...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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I solved the problem by change some decouple capacity of VCCPGM pin.But I have found it can't configurate sucessfully if TDO have no pullup resistor.

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Could u share the change things here?

Thanks

Jerry