JTAG ID code specified in JEDEC STAPL Format File does not match any valid JTAG ID...

Had this exact same problem. Here is what I did to correct it. I put a 1K Ohm resistor from TCK to Ground.

===========altera questions ===========

q:should tck be pulled up or down?

a:Since 2000, Altera devices have been designed for a pull DOWN resistor on TCK for both 3.3 and 5V devices.

(Most non-Altera devices tend to expect a Pull UP resistor on TCK)

Source: http :// www .ricreations. com/boundary-scan-faqs.html#altera_questions

(sorry about the formatting, new users can't post links/images, will correct this when I am more human.)

OP stated his/her device was a "EPM7128SLC84-15" - FPGA, but I am pretty sure its a CPLD, but what do I know, I am not human, yet.