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NKuma10's avatar
NKuma10
Icon for New Contributor rankNew Contributor
5 years ago

ISP clamp

Hi, We are using MAX 10 FPGA "10M40DAF484C7G" device in our project. Chip select for the Board management controller(AST 2600) is routed through this device which connects to the flash. As a result ...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI NKuma10,


I believe that the "CS" pin that is used to connect to the FLASH is actually a GPIO on MAX 10. So your concern is how to make it low during programming and in user mode?


Thank You.