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I am trying to use these family_jtags to connect our JTAG-supported soft modules(inside FPGAs), so we can access both vendor's JTAG component and our soft modules by software.
Your notes give the information about virtual jtag, but the component "family_jtag" is the primitive. What I really want to use is the primitive.
Is there any detailed information about this component's pinout?
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The *only* supported JTAG component is the SLD_Virtual_JTAG component. Altera's JTAG-to-Avalon components are internally constructed from a component that is essentially identical to this part too, eg., see these notes:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf I'm still not quite clear on your requirements:
1) If you have a JTAG-like component that you want to access, you need to connect it via the SLD_Virtual_JTAG component.
2) If you have a component with registers, then you can access it via a JTAG-to-Avalon-MM bridge, just provide your component with an Avalon-MM slave interface.
Can you please clarify.
Cheers,
Dave
Honored Contributor
