Forum Discussion

Honored Contributor

8 years ago

Is there a standard way for an FPGA Qsys system (Nios II) to access HPS pins?

Is there a standard method to connect FPGA side Qsys system Nios II to HPS pins and disable the HPS access to them? This needs to be done for UART, GPIO and Pushbuttons for Cyclone V SoC on the DE10-...

Altera_Forum

Honored Contributor

8 years ago

Preloader has to run. If you modify the preloader to sit in an infinite loop at the end rather than loading an image (and set BSP with watchdog disabled), you should be fine.

Forum Discussion

Is there a standard way for an FPGA Qsys system (Nios II) to access HPS pins?

Recent Discussions

Avalon-ST configuration with Agilex 3 fails

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Operating temperature for 10M08DCF256A7G

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Download links not working