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Altera_Forum
Honored Contributor
Honored ContributorIs there a standard way for an FPGA Qsys system (Nios II) to access HPS pins?
Is there a standard method to connect FPGA side Qsys system Nios II to HPS pins and disable the HPS access to them? This needs to be done for UART, GPIO and Pushbuttons for Cyclone V SoC on the DE10-...
Altera_ForumHonored Contributor
Honored ContributorPreloader has to run. If you modify the preloader to sit in an infinite loop at the end rather than loading an image (and set BSP with watchdog disabled), you should be fine.
