Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Is it possible to implement async ROM/RAM in Stratix family?

Hi, I need to have an asynchronous RAM/ROM in Cyclone IV E for my MIPS processor. Unfortunately, Stratix device family does not support LPM_ROM or LPM_RAM_DQ without providing the inclock/outcl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

--- Quote Start ---

>Are you really after a fully async ram, or just on the read side?

It's a single clock cycle processor, is async ram a bad design?

--- Quote End ---

It will really depend. Internal rams can do asynchronous read, but long path delays are going to decrease the maximum clock frequency possible. Synchronous is always better as it will always shorten the paths and increase the max frequency.