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Altera_Forum's avatar
Altera_Forum
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8 years ago

Is it possible to implement async ROM/RAM in Stratix family?

Hi, I need to have an asynchronous RAM/ROM in Cyclone IV E for my MIPS processor. Unfortunately, Stratix device family does not support LPM_ROM or LPM_RAM_DQ without providing the inclock/outcl...
Altera_Forum's avatar
Altera_Forum
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8 years ago

>Are you really after a fully async ram, or just on the read side?

It's a single clock cycle processor, is async ram a bad design?