Forum Discussion
Altera_Forum
Honored Contributor
8 years agoIP generated by Intel HLS Compiler is Missing Module IP in Platform Designer (Qsys)
Hi, Sorry for my poor English!!!:oops: -- Intel HLS Compiler (i++) can generate IP component for Platform Designer. I can make IP component by i++. I make my project in Quartus P...
Altera_Forum
Honored Contributor
8 years agothanks for reply !
I know Genreric Component's instantiation type to HLS, but I made IP by i++ in console. If using Generic Component's instantiaion type to HLS for use i++ IP in Qsys, we must regeneric IP one more. otherwise Is i++ in console for verify and simulation ?