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Altera_Forum's avatar
Altera_Forum
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18 years ago

invalid sof? please help me...

Hi, i am close to desperation because i am completely blocked with my work. I made a simple quartus design, a bdf including a 1s10 processor, compiled it and it reported no errors, programmed it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Unused pins are displayed with all other pins in fitter report. You could prevent from the said problem by setting unused pin default to input with weak-pullup or hold in device settings / "unused pins".

I would generally check, if the FPGA is configured with the intended design, e. g. by driving a test LED. I think, it could rather be an issue with Nios II configuration, but I can't help in this regard cause I'm not using Nios.