Honored Contributor
Honored ContributorThe code is for the ASMI parallel IP Core that is used to interface to the epcq. the datasheet for that is here https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altasmi_parallel.pdf (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altasmi_parallel.pdf)
per the data sheet for the asmi block I believe I am doing it right but I'm not getting the expected results. Here is a better picture of signal tap that shows the signals: https://www.alteraforum.com/forum/attachment.php?attachmentid=14493 In the image you can see I am asserting "wren" (write_enable) and "en4b" to enable 4 byte addressing then I assert "wren" and "write" to write to the epcq the value in data_in[7..0] (data inserted to epcq)to the address on addr_out[31..0]. finally I assert "rden" (read_enable) and "read" to read from the addr_out[31..0] register and I'm expecting to see the same bits on data_out[7..0] as data_in[7..0] after the read operation but I see FFh instead of the expected 10h. hopefully that makes sense. I'm still new to Verilog/altera so bare with me as I stumble my way through this.
