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emrahener
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3 years ago

Intel Agilex FHT / FGT lane swapping

Hi, We are using AGILEX AGIB027R31B2E2V FPGA . For Implementing 100 G Ethernet we utilize 4 FHT lane (4x25) Bank 13C Rx / Tx rx/tx_serial port Lane 0 connected to FHTR13C RX/TX CH0 . When I i...
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    emrahener
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    3 years ago

    Hi Pavee,

    How about 100 G Ethernet IP. Design including Ethernet IP implements when we have the reverse order. Can you comment on this ? Intel Dev Kits (Agilex I-Series Transceiver-SoC Development Kit) have different bit ordering for FHT implementations for different QSFP connectors.

    FGTR13A_TX/RX_Q0_CH0 =Serial RX_Tx <3>

    FGTR13A_TX/RX_Q0_CH1 =Serial RX_Tx <2>

    FGTR13A_TX/RX_Q0_CH2 =Serial RX_Tx <1>

    FGTR13A_TX/RX_Q0_CH3 =Serial RX_Tx <0>