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Altera_Forum
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15 years ago

integer data type

hello everyone, I need help here.Below is my vhdl code: LIBRARY ieee; USE ieee.ALL; ENTITY haar IS PORT ( clock : IN bit; clk : IN bit; -- Inputs in1 : IN integer RANGE...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

the code above is for short..Actually i obtain the based on the pipelined architecture that i has been designed.It consist of 3 stage and include 3 basic component.I try to troubleshoot the coding by simulate stage by stage,but the problem occurs is same..why?

Thanks for reply.