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Altera_Forum
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14 years ago

Input to Synchronizer/Metastability chain

Please see the attached pictures for diagrams of what I'm trying to do. I am currently crossing clock domains within my FPGA from a bus controller write enable signal to my other FPGA clock dom...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

set_clock_groups is meant to tell TimeQuest which clocks are unrelated and will not cut timing on individual paths. So the only thing that can be put into the groups are clock names. (If you haven't, go to alterawiki.com and there is a TimeQuest User Guide that talks about set_clock_groups, both in the Getting Started section and later on).