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Altera_Forum
Honored Contributor
Honored ContributorInput to Synchronizer/Metastability chain
Please see the attached pictures for diagrams of what I'm trying to do. I am currently crossing clock domains within my FPGA from a bus controller write enable signal to my other FPGA clock dom...
Altera_ForumHonored Contributor
Honored Contributoroops, I did not have the "Case Insensitive" box checked off when using the Clock Group GUI.
I was able to successfully generate the clock groups and looks like that solved my timing complaint! Thank you, you've helped me out greatly and now I know a little bit more about the power of Time Quest!
