Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorInformation on how to interface with RAM stick included with Stratix III DSP Devel
I had posted previously on how to get my design in DSP Builder to work in Quartus II with SignalTap II Logic showing 128k output instead of 8k. I finally found a way to get the design compiled in 16...
Altera_ForumHonored Contributor
Honored ContributorSignalTap can only use the FPGA's on-chip memory and won't use an external RAM chip. But why do you need to read so many output samples with signaltap?
