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Altera_Forum's avatar
Altera_Forum
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14 years ago

Information on how to interface with RAM stick included with Stratix III DSP Devel

I had posted previously on how to get my design in DSP Builder to work in Quartus II with SignalTap II Logic showing 128k output instead of 8k. I finally found a way to get the design compiled in 16...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

SignalTap can only use the FPGA's on-chip memory and won't use an external RAM chip. But why do you need to read so many output samples with signaltap?