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Altera_Forum's avatar
Altera_Forum
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15 years ago

inferring latch error

Hi, I'm new to VHDL and I am trying to set up a program that will take a 14 bit encoder input and output it to a 12 bit synchro converter. But the code must also create a gear ratio for the synchro ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Add a clock and also it seems that your 'if' statements have ony one condition and no 'else' condition...this some time infer latches to your design...