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Altera_Forum
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13 years ago

Indefinite states of State Machine - VHDL

Hi Guys, I would like to ask for your help... I wrote a simple code that is identifying the rising edge of incoming signal. There are two states - every time that rising edge existing, the st...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The passing of Incoming Signal through FF was the brilliant idea. The code is working without Indefinite states.

Thanks to all.