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Altera_Forum
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13 years ago

Indefinite states of State Machine - VHDL

Hi Guys, I would like to ask for your help... I wrote a simple code that is identifying the rising edge of incoming signal. There are two states - every time that rising edge existing, the st...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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Hi deded84,

I’m not sure if I understand you right. But if your code sometimes works and sometimes not, it sounds like metastability. Is the external signal synchronized in by flip flops? You should always use synchronizers for external asynchronous signals.

Here is a good paper about this topic:

http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf?gsa_pos=9&wt.oss_r=1&wt.oss=metastability

Greets

Sim

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Thanks for an answer,

I think that you are right...will check and inform you :)