In the Stratix 10 Clocking User Guide (Dec 2018) section 2.1.4.1.3 on page 11 describes a way to get the clocks coming out of the I/O PLL. But I don't see how I enable this functionality in the I/O PLL parameter editor. How do I turn on this feature?

In Figure 5 of the Stratix 10 Clocking and PLL Architecture document (see below) I wanted to know how to enable the I/O PLL Clock Gates shown in the block on the left. I thought the Distributed Sector Level setting controlled the clock gates in the SCLK block on the right. Figure 5 shows three different clock gates (I/O PLL Clock Gates, Root Clock Gate, Clock Gate in the SCLK section) but I only see two choices in the Clock Control IP.