Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

In-System Programming with Cyclone III

Hello, I have a custom board that uses the Cyclone III (EP3C40 - 240 pin) FPGA. The board has two headers for connecting to the ByteBlaster II. One of the headers is used for JTAG configuration...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I've finally gathered some needed equipment which includes a digital oscope (and finally a decent DMM). Here's what was measured for pins:

-nSTATUS has a 3.4Vpp signal with 80% duty cycle and freq of 3.58 kHz.

-nCONFIG floats at 3.3V high shortly after applying power

-CONF_DONE stays low (some noise with about 25mVpp centered at 0V)

So it looks like the MSEL (and by the way these are set with High at 2.5V, thanks again for clearing up the confusion) does set up the AS mode but the configuration does not complete. I let the board stay on for a good couple minutes just to be sure that I waited long enough to allow configuration to complete, but these signals remained constantly at the states mentioned above.

Just to note aside, I checked the trace for the CONF_DONE pin just to be sure there wasn't a lifted trace. It is solid.

Any further suggestions to look for? I'll have to read up on the behavior of the nSTATUS pin; does this measurement sound odd at all?

Thanks!