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Altera_Forum
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13 years ago

Implementing 18-bit lvds serializer in CPLD

Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Cyclone FPGAs are specified to support 450 MHz input clock, but restriction related to IO standards might apply.

I can still hardly imagine that a high-speed serial interface device uses 450 MHz clock output without good cause. None of the popular serial interface standards is exposing a bit rate clock output.