Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorImplementing 18-bit lvds serializer in CPLD
Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_ForumHonored Contributor
Honored ContributorCyclone FPGAs are specified to support 450 MHz input clock, but restriction related to IO standards might apply.
I can still hardly imagine that a high-speed serial interface device uses 450 MHz clock output without good cause. None of the popular serial interface standards is exposing a bit rate clock output.
