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Altera_Forum
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13 years ago

Implementing 18-bit lvds serializer in CPLD

Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Again, Good one! I don't even need to recover the clock I can actually get an optional shift clock line to take it from. So theoretically that simplifies things a lot.

Only thing I would need to have is:

- An LVDS input (or combine 2 single ended inputs?)

- A decoder, which is probably something in between of UART and SPI.

Is there a standard on how the encoding is usually done? I mean, number and level of start bits and stop bits? Or is this device specific?

This particular image sensor has one start bit (1) and one stop bit (0).