I'm implementing a Math Equation on my FPGA, am I following the right methodology?

Because it is a SOC, much of the DE1-SOC material centers around getting the ARM HPS running Linux etc. If you are comfortable with that (software background?) you would benefit from getting your board up and running to that point. While you can have a NIOS-II, I would not suggest that unless you are not comfortable at all with the ARM+Linux approach usually used on that board.

Without knowing anything about your algorithm or background, a kind of "natural" system would be one where your Linux application software takes care of all of the PC data transfer and populating buffers in memory.

The first generation of your Qsys component for your math block could simply implement an Avalon-MM control port, where one control register receives the data one-write-at-a-time and another control register is where the result is posted.

If your goal is to avoid software at all costs and focus on the HDL development of your math block, I would suggest just using an Avalon-MM control port in your component, and then using the JTAG-Avalon-MM Master component along with system-console on your PC to do your read/writes and maybe TCL script.