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Thank you for your help.The negative slack and critical warning has been dismissed.
Scaling the PLL down to 150MHz according to your idea also get setup failure(in slow 1200mv 85c model).So I was compelled to give in to the 133.333MHz,and then all right.
The slow 1200mv 85c model Fmax=142.29MHz,
The slow 1200mv 0c model Fmax=152.63MHz.
I wish to work stable in 133.333MHz clock which can synchronous to the DDR2 SDRAM---my next objective.
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I am suffering from the same critical warning regarding the timing requirement not met.
I am implementing an Ethernet connection on Cyclone III development board.
All clocks, inputs & outputs are constrained. I tried to decrease the system clock to 133.333 (as you suggested), but still having this critical warning
Can any one help me in this issue.
Thanks & Regards
Honored Contributor
