Honored Contributor
Honored ContributorHello vlsidc (http://www.alteraforum.com/forum/member.php?u=28388):tms, tdo, tdi, and tck are the JTAG pins. BadOmen said the template will be fixed in the next version I think. Try this instead:
set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms] set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo] Using 1 is overkill since the dev kits don't have that much board delay, I just picked it at random.------BadOmen. I've eliminate critical warning (timing requirement not met) in my final sdc file,like this: derive_pll_clocks -create_base_clocks set altera_reserved_tck {altera_reserved_tck} set_clock_groups -exclusive -group [get_clocks $altera_reserved_tck] -group [get_clocks "$ddr2bot_auxhalf_75 $ddr2bot_sysclk_150"] -group [get_clocks "$ddr2top_auxhalf_75 $ddr2top_sysclk_150"] # jtag interface set_input_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports altera_reserved_tms ] set_input_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports altera_reserved_tdi ] set_output_delay -clock [ get_clocks $altera_reserved_tck ] 10 [ get_ports altera_reserved_tdo ] ---good luck!
