I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

Those warnings about keepers not being matched are fine. That just means the constraints are in place but the logic is not present in the final hardware image. I need to see the worst failing paths. In timequest there is a macro available that'll list the top failing paths. It'll probably be limited to 200 paths but I need to see the top few otherwise I can't tell what paths need additional constraints. The listing will have the to and from nodes as well as the launch and latch clocks (both should be the JTAG clock). I typically don't need to constrain these paths since I have all the necessary IP licenses which avoids the open core plus logic. In your design the open core plus logic has this name: "pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967" and is generated only when you do not have a valid license for the ip in your system. From compile to compile I'm not sure if that logic name stays constant which could make it difficult to constraint.