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Altera_Forum
Honored Contributor
16 years agoTry this:
derive_pll_clocks -create_base_clocks set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi] set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms] set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo] The first line will make sure that there is a clock called 'altera_reserved_tck' in your system and the last three lines will be constrained with respect to this clock. Usually I set these long clock names to short names names using variables. Then you can refer to the variable using $<variable name> set Short_Name <really long hierarchy name for signal/clock> Since reset_n into the system must be held low for a two or more cycles I normally cut the reset_n input pin. On the dev kits the reset_n signal is hooked up to a push button so the reset will occur for many cycles. Inside the SOPC Builder system reset_n is synchronized to each clock domain in your system. Usually I don't attempt to tackle recovery/removal timing violations until my design meets setup and hold times and all my I/O are constrained. Usually the recovery and removal timing violations can be resolved by additional constraints around the reset synchronization logic.