I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

Dear BadOmen:

Recently,I'm struggling with the DDR2 HP Controller under the direction of AN517(Using High-Performance DDR, DDR2, and DDR3 SDRAM With SOPC Builder).The design is targeted to the Cyclone® III EP3C120F780C7 Kit.

In this example,the SOPC system contain a Half-Rate DDR2 Controller working at 150MHz(altmemddr_auxfull),the PLL of the controller simultaneously generate a 75MHz output clock(altmemddr_sysclk) which been used as SOPC system clock.

After compilation,I got three critical warning again------also cause by JTAG.The TimeQuest report negative slack(-2.428) in Summary(Removal) of altera_reserved_tck.

I lose my head of this because I've constrained the JTAG using the templet:# JTAG Signal Constraints constrain the TCK port

create_clock -name tck -period 100.000 [get_ports altera_reserved_tck]# Cut all paths to and from tck

set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port

set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port

set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port

set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]

I didn't know what's wrong with it.

An other problem is the unconstrained path cause by the reset_n(cpu reset pin).My constraint code below this:

set_input_delay -add_delay -max -clock [get_clocks

{inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|pll|altpll_component|

auto_generated|pll1|clk[0]}] 2.0 [get_ports {reset_n}]

set_input_delay -add_delay -min -clock [get_clocks

{inst|the_altmemddr|altmemddr_controller_phy_inst|altmemddr_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|pll|altpll_component|

auto_generated|pll1|clk[0]}] 1.0 [get_ports {reset_n}]

In my mind,the reset_n should be constrained by the system clock(altmemddr_sysclk,75MHz),I got it's name from the Clocks Summary of TimeQuest.

But in the compilation warning,the constraint code was ignored assignment because the Argument -clock is an empty collection.

It means the clock name was wrong.

How can I get the correct system clock name generate by the PLL of DDR2 HP Controller?