Forum Discussion
Altera_Forum
Honored Contributor
16 years agoThank you for your help.The negative slack and critical warning has been dismissed.
Scaling the PLL down to 150MHz according to your idea also get setup failure(in slow 1200mv 85c model).So I was compelled to give in to the 133.333MHz,and then all right. The slow 1200mv 85c model Fmax=142.29MHz, The slow 1200mv 0c model Fmax=152.63MHz. I wish to work stable in 133.333MHz clock which can synchronous to the DDR2 SDRAM---my next objective.