I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

The setup failures are probably real timing violations. You are using a -7 speed grade so it might be difficult to hit 167MHz depending on your design. I would scale that clock down to 150MHz then start optimizing from there.

Recovery failures have typically come having the PLL instantiated within my SOPC Builder system. This is a result of a clock crossing adapter being placed in front of the PLL slave port. I normally instantiate my PLLs outside of SOPC Builder for this reason. A recovery failure is similar to a data setup time violation only instead of data it has to do with the reset of a flip flop.... I hope that makes sense, I'm not very good at explaining timing analysis. Using the latest SOPC Builder I have noticed fewer cases where recovery/removal timing violations occur during analysis.