I want to know the max speed of NIOS ii based on cyclone iii EP3C120N780C

Thank you,BadOmen!

Your codes are working.All unconstrained paths has been cleared!

After Report All Summaries,the report pane of TimeQuest display 2 red warning:

1)Summary (setup)

Clock slack end point TNS

inst|the_altpll_0|altpll1|pll3|clk[0] -1.167 -131.807

2)Summary(recovery)

inst|the_altpll_0|altpll1|pll3|clk[0] -5.900 -78.992

To constraining PLL,I place this code in the .sdc file:

create_clock -name {clk_50mhz} -period 20.000 -waveform { 0.000 10.000 } \[get_ports {clk_50mhz}]

derive_pll_clocks

derive_clock_uncertainty

The input clock of the altpll is 50mhz,and output clock is 166.7mhz

I don’t understand where the negative slack come from,and how to eliminate it.

After compilation ,I receive 3 critical warning(Timing requirements not met) because of this.