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Altera_Forum
Honored Contributor
Honored ContributorI have too often read how made Asynchronous signals e.g clear, set e.t.c are but than
... why is it that Altera primitives even have asynchronous clear and set signals on them. If latches are so bad, why does Altera even have them in the first place in Quartus? Also if ripple count...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The point I wish to get to is that, the tools we have in the industry are not inclined towards this, they abhor asynchronous behavior. Why? --- Quote End --- It's not primarly a limitation of the tools. It's the present FPGA hardware that's constructed to achieve best performance in synchronous designs and that demands for tools supporting it. Presuming that the claimed advantage of asynchronous circuits in terms of power consumption holds, it would need different hardware and tools to implement it in the FPGA worlds.
