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Altera_Forum
Honored Contributor
Honored ContributorI have too often read how made Asynchronous signals e.g clear, set e.t.c are but than
... why is it that Altera primitives even have asynchronous clear and set signals on them. If latches are so bad, why does Altera even have them in the first place in Quartus? Also if ripple count...
Altera_ForumHonored Contributor
Honored ContributorI'm not sure what you mean on the first statement. Clock muxing is usually done to switch between different clock sources, while clock gating can be done for power. The example you provide can be done with the enable on the altclkctrl block, which can be timed in a synchronous manner, so that turning the clock on/off is a completely synchronous process and there is no "asynchronous" behavior. The key is to design synchronously when you can, and to be careful and know what you're doing when designing asynchronously. Is there a specific circuit/scenario you're trying to analyze?
