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Altera_Forum
Honored Contributor
Honored Contributori do'nt want to remove redundant logic...
i want to implement ring oscillator with NOT gates but when i synthesize it, the synthesis tool remove the redundant logic, but my requirement is to keep redundant logic.. so plz someone help me to s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- you r right ..... i m using it for delay...... thank u.... ok , i'll try xilinx forum.. thanks --- Quote End --- Please note that using logic cells for delays is not reliable, whatever technology you use. edit - But its probably useful for an oscilator! :rolleyes:
