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Altera_Forum
Honored Contributor
Honored Contributori do'nt want to remove redundant logic...
i want to implement ring oscillator with NOT gates but when i synthesize it, the synthesis tool remove the redundant logic, but my requirement is to keep redundant logic.. so plz someone help me to s...
Altera_ForumHonored Contributor
Honored ContributorThe question actually makes sense for creating logic cell delays, Altera has synthesis attributes for this purpose. Possibly Xilinx has similar means.
