I am getting a hold violation using the on chip flash ip. What can I do to resolve this issue?

I want to constrain most of my outputs to 1 - 25Mhz clock period (40 ns). With the min and max set to 0 & referenced to the virtual 25 mhz clock, this is assured. And for this device, it shouldn't be a problem. My worst case setup slack is 14 ns to my outputs and worst case hold slack is 1.7ns. So, I'm meeting that by a pretty large margin.