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KLohr's avatar
KLohr
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

I am getting a hold violation using the on chip flash ip. What can I do to resolve this issue?

It's from avmm_data_read to an internal node in the ip: -0.060 motor_ctrl:loop1|ufm_stmac:ufm_stmac|data_read motor_ctrl:loop1|ufm_stmac:ufm_stmac|max10_ufm:max10_ufm|altera_onchip_flash:onchip_flas...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Having a max and min of 0 for your output delays doesn't make any sense and could be part of the problem. But are these outputs driving something that has setup and hold requirements (doesn't look like it). If not, you should use false paths on the outputs instead of set_output_delay.

Does your design not have any inputs?

#iwork4intel